Semiconductor packaging becomes increasingly difficult as the size of devices becomes smaller and as packages increase in complexity, such as those including multilayer vertically stacked semiconductor chips. In particular, electrical connections between devices and to external power supplies become more challenging.
Conventional processes for forming electrical contacts typically involve expensive photolithography and etching to expose a thin bonding pad. Such a technique is described in U.S. Pat. No. 7,808,064. However, etching can sometimes thin or otherwise damage the bonding pad, leading to an unacceptably high device rejection rate.
In other known processes, laser drilling is used to form a void through a thin bonding pad. This is shown in US 2010/0230795. However, subsequent metallization results in an extremely small area of contact between the metallization and the bonding pad; only an annular ring of metallization contacts an annular ring of the thin bonding pad. This small area of contact can lead to device failure, particularly if the metallization does not make good contact with the annular ring of the bonding pad.
Thus, there is a need in the art for improved electrical contacts in multilayer microelectronic device packages that are reliable and easy to fabricate.